1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device using selective epitaxial growth, by which leakage current caused by a contact between a device and metal is prevented from occurring.
2. Discussion of the Related Art
Generally, as patterns of semiconductor devices are getting more finely reduced and more highly integrated, it becomes increasingly necessary to reduce a size of a wiring contact. Yet, the contact size cannot be reduced indefinitely due to the limitation of an aspect ratio of the contact.
It is highly probable that a contact intrudes an isolation area (STI) in such modern devices. Hence, an interface between silicon and oxide is vulnerable to leakage current.
FIG. 1A shows a cross-sectional diagram of a contact according to a related art, in which a portion bisected along a line A–A′ in FIG. 1B is shown.
Referring to FIG. 1A, in an area WELL A, when a contact 1 is formed, an interface between an STI oxide layer and STI silicon is vulnerable to various processes such as cleaning, etch, silicidation, and the like. Hence, the contact 1 may be formed deeper than is shown in the drawing.
In a case where the contact intrudes the STI interface, as shown in the area WELL A, a distance between a junction and substrate 2 becomes shorter, thus giving rise to leakage current.
FIG. 1C is a magnified cross-sectional diagram of a contact according to a related art.
Referring to FIG. 1C, in case of STI (shallow trench isolation), a device isolation property is excellent. Yet, a contact hole 1 intrudes into the STI boundary to trigger the leakage current. The shorter the distance 3 between the contact and junction, the more likely sizable leakage current is generated. And, FIG. 2A and FIG. 2B are real photos of contacts according to the related art.
To overcome the above-mentioned problem, selective epitaxial growth, (SEG) which is disclosed in Korean Patent Application Laid-Open Nos. 2001-73705, 2001-45423, or 2001-10442, is employed.
In Korean Patent Application Laid-Open No. 2001-73705, a method of growing SEG between a substrate and contact area is disclosed, in which a contact area is increased to secure a recess margin for overetch and to lower contact resistance.
However, as a width of a device is reduced, a contact is overlapped with a device isolation layer. Hence, it is unable to improve the problem of leakage current occurring.
In Korean Patent Application Laid-Open No. 2001-45423, SEG is employed as a design rule is further reduced to prevent a wordline and semiconductor substrate from being damaged by a contact etch prior to forming a contact.
However, there is no thickness difference between the SEG and gate. Consequently, the SEG is too thick for effectively fitting in a nano-sized and highly integrated semiconductor device.